1. Field of the Invention
The present invention generally relates to a method of fabricating a circuit substrate. More particularly, the present invention relates to a method of fabricating a circuit substrate with two metal layers simultaneously electroplated on the both sides of the substrate.
2. Description of the Related Art
Printed circuit boards (PCB) that can be bonded with various electric devices are widely utilized in the electronic industry. After the integrated circuit (IC) and the computer system with complex and fine circuitry are presented to the public, the printed circuit boards with a single circuit layer can not provide sufficient layout space and thus the printed circuit boards with double or more circuit layers are successively turned up. Printed circuit boards can serves as a main board of a computer system or as a circuit substrate for packaging chips.
Generally, the printed circuit board comprises multiple patterned circuit layers and at least an insulation layer. The insulation layers are arranged respectively between the neighboring patterned circuit layers. There are multiple vias penetrating through the insulation layers and connecting the patterned circuit layers positioned on the upper and lower sides of the insulation layer. A chip can be electrically connected to a circuit substrate through bumps or conductive wires, and further, can be electrically connected to external devices through the internal circuitry of the substrate and the contacts, such as solder balls or pins, positioned on the lower surface of the substrate.
As far as a wire-bonding and ball-grid-array type of chip package is concerned, the chip package includes a circuit substrate having multiple pads formed on the upper surface thereof for jointing with conductive wires and formed on the lower surface thereof for jointing with solder balls. It should be noted that the circuit layer is generally made of copper. In order to avoid oxidation of the pads made of copper and to enhance the reliability and yield of connecting conductive wires onto the pads, metal layers, such as Ni/Au layers, are generally electroplated on the copper layer.
For electroplating metal layers on the pads, plating lines are formed on the peripheral areas of the circuit substrate. The metal layers are electroplated on the pads by providing an electrical current flowing through the plating lines. In the above technology, only if the plating lines are arranged on the circuit substrate, the electroplating processes can be conducted. However, the plating lines occupy the layout area of the circuit substrate and thereby the circuit substrate has lower layout density. Moreover, after the electroplating processes, the plating lines should be cut. Even though the plating lines have been cut, the plating lines can not be completely eliminated and stubs still remains on the circuit substrate. When electric current flows through the circuit line jointed with the stubs, noise will be dramatically generated and thereby the circuit has a lower electric effect.
In order to solve the above problem, a method of electroplating metal layers on both sides of the circuit substrate is being developed without the plating lines. In this method, two conductive seed layers are formed respectively on both sides of the circuit substrate. Two patterned photoresist layers are formed respectively on the conductive seed layers positioned on both sides of the circuit substrate and have openings exposing the conductive metal layers. An electrical current is applied to flow through the conductive seed layers to electroplate metal layers on the conductive seed layers positioned on both sides of the circuit substrate. The metal layers are formed on the surface of the exposed conductive seed layers. The above mentioned electroplating process is inefficient and time-consuming.
In order to solve the above problem, chemical-plating processes have been proposed for plating the metal layers. However, the metal layer plated using such chemical plating processes is very thin and has unstable electrical properties.